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[VHDL-FPGA-VerilogDDR_sdram

Description: 文件里有DDR3/DDR4 sram的verliog模型,而且具有DDR4参考书(The document has a verliog model of DDR3/DDR4 SRAM, and it has DDR4 reference books.)
Platform: | Size: 4935680 | Author: maxw123456789 | Hits:

[Technology ManagementDDR4 JEDEC standard

Description: DDR4 SDRAM Specifications from JEDEC STANDARD. ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for x4, x8, and x16 DDR4 SDRAM devices. This standard was created based on the DDR3 standard (JESD79-3) and some aspects of the DDR and DDR2 standards (JESD79, JESD79-2).
Platform: | Size: 1824071 | Author: bdebug@gmail.com | Hits:
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